1. Field of the Invention
This invention relates to a method and apparatus for designing circuits and in particular to a method for designing integrated circuits according to a hierarchical block-based design method.
2. Related Art
As circuit design environments become increasingly competitive there is increasing pressure to bring devices implementing the circuits to market quickly and profitably. Todays sub micron technologies may employ processor cores, general purpose circuit blocks and dedicated functional units designed specifically for the intended applications. Integrated circuit designs frequently also include analog circuit blocks such as analog to digital converters, digital to analog converters and phase locked loops. The resulting circuit may incorporate several million gates and would typically operate at clock speeds above 100 MHz. Unnecessary delays in timing convergence or chip assembly are undesirable and can turn out to be costly. Integrated circuit designers working at sub micron dimensions face challenges in implementing and optimizing working chips of such complexity. Circuit design presents considerable difficulties in managing physical implementation to achieve timing convergence. A conventional design process begins with logic synthesis followed by a physical design phase employing place and route procedures. Problems solved during the place and route procedures often require modifications to be made in a further logic synthesis stage and vice versa. Typically iterations through logic synthesis and physical design stages are required.
The definition of a block varies. However in general a block may be regarded as a circuit element comprising anywhere from an individual cell or several cells upwards to thousands of cells. Block-based design methods have been developed to reduce the number of iterations required between logic synthesis and physical implementation stages of integrated circuit design flow. These design methods might employ automatic software tools to generate candidate floorplans for implementing the integrated circuit. The floorplanning tools are integrated with a range of other software tools for designing detailed circuit implementations within each block. Designers can build a floorplan for the integrated circuit by defining high-level descriptions of the blocks. In practice, this is done either by generating new views of blocks or by re-using proven design blocks from previous designs. Block-based design environments allow integrated circuits to be defined in terms of blocks, sub-block descriptions, or actual layouts with parasitics.
Block-based (or hierarchical) design flows reduce the number of iterations required between logical synthesis and physical implementation stages of chip design. Thus in any given design process, a great deal of the time saved is achieved through the use of these automated software tools for designing and updating floorplans. The advantage is that block-based design flows enable concurrent development of the high level design and the individual blocks which make up that design. A problem with existing block-based design flows is that it is difficult to complete blocks of a chip design and join them together, without knowing the detailed internal physical implementation of each block. One reason for this is that silicon MOS devices can be damaged during their fabrication by what is known as the xe2x80x9cantenna effectxe2x80x9d. Charge which accumulates on exposed metal surfaces (for example during etching processes) can be discharged through MOS gate material which causes yield loss or failures of the silicon product. Circuit design rules include a set of rules which, if followed, protect the circuit from antenna-related problems. Design flows usually include a verification step which checks that these antenna rules have been complied with.
For MOS process technologies, the antenna effect is caused by charge induced sequentially by and in proportion to the amount of exposed metal track connected to a MOS gate at each photo/etch stage. Modem MOS processes use a number of metal interconnect layers and the amount of exposed metal at each metal etch stage is a useful indication of damage probability. Whenever blocks are joined together in block-based design flows, gates within a block can be damaged by antenna effects of the exposed metal external to the block. The charge accumulates at the metal making the internal connection from the port to the MOS gate. Known design flows cannot prevent antenna failures of this type without knowledge of the detailed characteristics of internal and external metal tracking and the amount of gate material connected within a block. Unfortunately this information is not always available early enough in the design process and the result is an antenna failure during high-level design checks. This requires another iteration of the design process, possibly involving an iteration of the sub-block level design. Antenna fails of this type can lead to a significant delay in chip design processes, and due to the random nature of automated place and route flows these iterations may not be convergent towards a solution.
This invention seeks to provide an improved method and apparatus for circuit design with particular applications in integrated circuit design.
According to an aspect of the present invention there is provided a method for designing multi-layer electronic circuits, the method including a block-based physical design stage. The design method includes defining a plurality of circuit blocks in terms of physical boundaries, the plurality of circuit blocks including a first circuit block with at least one port for connecting to a portion of inter-block routing comprising conducting material external to the first circuit block. The method further provides protective routing for the at least one port of the first circuit block in a region between the block and the inter-block routing, wherein circuitry within the first circuit block and connected to the at least one port is not in-circuit with the conducting material of the inter-block routing during processing steps involving conducting material.
In one aspect of the invention, providing the protective routing includes the step of connecting the at least one port to a portion of a conducting layer which is higher in the multi-layer structure than the highest conducting layer used for routing the net containing the at least one port for inter-block routing.
Another aspect of the invention provides a method of circuit design for a multi-layer circuit. The design method includes defining one circuit block of a plurality of circuit blocks, the one circuit block having a port for connecting a portion of the one circuit block to inter-block routing. Routing layers are determined in the plurality of circuit blocks that are connected to the port of the circuit block. A bridging layer is selected that is a conducting layer of the multi-layer circuit, where the bridging layer is higher than any routing layer connected to the port of the circuit block. The port of the circuit block is connected to the bridging layer using a first interlayer connection, and the bridging layer is connected to the inter-block routing using a second interlayer connection.
Another aspect of the invention includes a multi-layer circuit that is designed according the method described herein. The multi-layer circuit includes a first circuit block having one or more first routing layers and a first port connected to at least one of the first routing layers. Inter-block routing connects the first port to another circuit block of the multi-layer circuit. A halo region connects the first port to the inter-block routing. The halo region includes a second routing layer that is higher than any routing layer in the first circuit block and the second circuit block that is connected to the first port and the inter-block routing. A first interlayer connects the first port to the second routing layer, and a second interlayer connection connects the second routing layer to the inter-block routing. A portion of the second routing layer between the first interlayer connection and the second interlayer connection is isolated from the rest of the second routing layer to form a bridge between the first interlayer connection and the second interlayer connection. Since the second routing layer is on a higher layer of the multi-layer circuit than the first routing layers, the antenna effects are mitigated and the gates in the first circuit block are protected during the fabrication process.
The halo region can be repeated for each port of the circuit block(s) in a multi-layer circuit. The protective halo therefore ensures independent blocks are electrically isolated from each other during the critical processing steps which have the potential to cause failure due to antenna related effects. Designers can therefore complete blocks in advance of them being connected together, without knowing the detailed characteristics of the antenna tracking or the amount of gates connected to tracks outside of each of the blocks. Another advantage of the technique is that antenna problems caused by inter block routing interacting with existing block level routing can be solved even if it is not possible to modify the internal block routing, e.g., in an imported hard macro block. This can often be the case if sub-block level designs are designed by third parties.
Another aspect of the invention includes a computer program product embodied on a computer program medium having computer program code for designing a multi-layer circuit. The computer program code includes a means for causing a computer to define a plurality of circuit blocks, each circuit block having one or more routing layers and at least one port. The computer program product further includes a means for causing the computer to define a net from the plurality of circuit blocks, the net having a plurality of the ports from the plurality of circuit blocks that are to be connected by the inter-block routing. The inter-block routing further includes a means for causing the computer to determine a bridging layer for one port of the plurality of ports, the bridging layer being a conductive layer that is higher than any routing layer on the net that is connected to the one port.
Additional advantages and novel features of the invention will be set forth in part in their description which follows, and in part will become apparent to those skilled in the art upon examination of the following and the accompanying drawings. The features and advantages of the invention may be realized and attained by means of the various apparatus definitions and method steps, particularly pointed out in the appended claims.